This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2002-156191 filed May 29, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as a flash memory and a data-write method thereof.
2. Description of the Related Art
In a flash memory, data is stored by changing the threshold voltage of the floating gate of a memory-cell transistor by changing the amount of charge stored therein through erase and write operations. For example, data xe2x80x9c1xe2x80x9d is stored by releasing electrons from the floating gate, thereby allowing the threshold to be negative and data xe2x80x9c0xe2x80x9d is stored by injecting electrons.
In a NAND flash memory, data 1 or 0 is distinguished by supplying, for example, 0 V, to a word line of the memory cell selected in a readout operation. A plurality of unselected memory cells is connected in series to the selected memory cell. Therefore, for example, 4.5 V, is supplied to the word lines of the unselected memory cells to bring the unselected memory cells into an electrically conductive state independently of the data stored therein. Therefore, the threshold of the memory cell to be written during a write operation must be sufficiently controlled so that it falls within the range of 0 to 4.5 V.
Therefore, to control the threshold voltage of a memory cell during the write operation, the commonly used data write method employs a xe2x80x9cstep-up write voltagexe2x80x9d. Such a data write method is described in Fast and Accurate Programming Method for Multi-level NAND EEPROMs, pp 129-130, Digest of 1995 Symposium on VLSI Technology.
The data write method using the xe2x80x9cstep-up write voltagexe2x80x9d employs the following characteristic feature: when the write voltage to be supplied to a memory cell is increased at a predetermined rate (e.g., 0.2 per 10 xcexcsec), the threshold voltage increases at the same rate (e.g., 0.2 per 10 xcexcsec). Further in this method, the threshold voltage of each memory cell is detected at intervals of 10 xcexcsec and when the threshold voltage reaches a predetermined write verify voltage, the write operation is inhibited. In this manner, the threshold voltage is controlled so that it falls within a margin 0.2V above the write-verify voltage.
In the method mentioned above, the write operation is controlled by using the feature that the threshold voltage increases at a constant rate. Therefore, before the verify operation is initiated, a so-called pre-write operation is performed by setting the initial write voltage to a sufficiently low value in order to increase the threshold voltage at the constant rate in advance.
A semiconductor integrated circuit device according to a first aspect of the present invention comprises:
first and second electrically rewritable nonvolatile semiconductor memory cells; and
a write control circuit, which supplies a plurality of programming pulses simultaneously to the first and second memory cells, the write control circuit supplies:
a first pre-programming pulse simultaneously to the first and second memory cells independently of the write statuses thereof;
a second pre-programming pulse, after the supply of the first pre-programming pulse, simultaneously to the first and second memory cells independently of the write statuses thereof, the second pre-programming pulse having a potential higher than the first pre-programming pulse by a first potential difference; and
staircase programming pulses, after the supply of the second pre-programming pulse, simultaneously to the first and second memory cells, the staircase programming pulses having an initial voltage lower than the second pre-programming pulse and increasing the voltage at a rate of a second potential difference per pulse, the second potential difference being smaller than the first potential difference.
A method of controlling a write operation of a nonvolatile semiconductor memory device according to a second aspect of the present invention comprises:
supplying a first pre-programming pulse simultaneously to first and second memory cells that are connected to a common word line and discrete two bit lines independently of the write statuses of the first and second memory cells;
supplying a second programming pulse, after the supply of the first pre-programming pulse, simultaneously to the first and second memory cells independently of the write statuses thereof, the second programming pulse being higher than the first pre programming pulse by a first potential difference;
supplying a staircase programming pulses, after the supply of the second pre-programming pulse, simultaneously to the first and second memory cells, the staircase programming pulses having an initial voltage lower than the second pre-programming pulse and increasing the voltage nearly at a rate of a second potential difference per pulse, and the second potential difference being smaller than the first potential difference; and
inhibiting a write operation to a memory cell that has been detected to reach a predetermined write status during supply of the staircase programming pulses.